1. Field of the Invention
The present invention relates to a method for fabricating a capacitor of a semiconductor device, and more particularly to a method for fabricating a capacitor which can secure a capacitance suitable for a high-integrated semiconductor device and also can improve the safety of a pattern.
2. Description of the Prior Art
According to the advance of high integration of the semiconductor device, capacitors fabricated in a cylinder shape by the conventional process have a limitation of capacitance security.
As a cell pitch is reduced, the sectional area of a capacitor is reduced, and thus the height of the capacitor must be increased more and more in order to compensate for the reduced sectional area.
However, with the consideration of pattern formation, even the increase of the height has a limitation. Also, it has been difficult to prevent the inclination of a storage nodes when a cylinder shape is formed.
Hereinafter, a method for fabricating a capacitor of a semiconductor having such problems, according to the prior art, will be described with reference to FIGS. 1A to 1H.
FIGS. 1A to 1H are cross-sectional views showing each process of a method for fabricating a capacitor of a semiconductor device according to the prior art.
As shown in FIG. 1A, with a method for fabricating a capacitor of a semiconductor device according to the prior art, bit lines 13 and a hard-mask layer 15 are formed on a semiconductor substrate 11 having a device isolation film and word lines, and then an interlayer insulating film 17 is deposited on the upper surface of the resultant lamination obtained through the above process.
Then, after portions of the interlayer insulating film 17 are selectively removed to form plug contact holes 19 which exposes portions of the semiconductor substrate 11 between the bit lines 13, contact plugs 21 are formed in the plug contact holes 19.
Subsequently, a first nitride film 23 for an etching barrier is deposited on the upper surface of the resultant lamination obtained through the above process, and then a first interlayer oxide film 25 is deposited on the first nitride film 23.
Next, as shown in FIG. 1B, a mask pattern (not shown) for defining a storage node formation region is formed on the first interlayer oxide film 25, and then the first interlayer oxide film 25 and the first nitride film 23 are sequentially removed using the mask pattern (not shown) as a mask, and thereby storage node contact holes 27 are formed.
Subsequently, as shown in FIG. 1C, the mask pattern (not shown) is removed, and then a polysilicon layer 29 for storage nodes is deposited on the surface the resultant lamination including the storage node contact holes 27.
Next, a second interlayer oxide film 31 is deposited on the polysilicon layer 29 for storage nodes with a thickness enough to fill the storage node contact holes 27, and chemical mechanical polishing (CMP) is performed to separate and flatten the second interlayer oxide film 31.
Subsequently, as shown in FIG. 1D, the first interlayer oxide film 25 and the second interlayer oxide film 31 are removed to form storage node electrodes 29a of a cylinder shape. At this time, as shown at “A” in FIG. 1E, a bridge is formed between the storage node electrodes 29a of a cylinder shape due to an inclination problem caused when the storage node electrodes 29a are formed.
Next, as shown in FIG. 1F, a dielectric film 33 is deposited on the surface of the storage node electrodes 29a. 
Subsequently, as shown in FIG. 1G, a polysilicon layer for a plate is deposited on the dielectric film 33, and then this polysilicon layer is flattened to form a plate electrode 35 of a capacitor.
Subsequently, as shown in FIG. 1H, another interlayer insulating film 39 is additionally deposited on an interlayer insulating film 37 including the plate electrode 35, and then the interlayer insulating film 39 is selectively removed to form wiring contact holes 41 which expose the plate electrode 35.
Next, wiring plugs 43 electrically connected with the exposed plate electrode 35 are formed in the wiring contact holes 41, and then a metal wiring 45 is formed on the wiring plugs 43.
In the conventional method described above, when storage node electrodes of a cylinder shape as shown in FIG. 1D are formed by removing an interlayer oxide film, it is either impossible to employ metastable polysilicon (hereinafter, referred to as “MPS”) or inevitable to use the MPS only inside of the cylinder, in consideration of step coverage of dielectric materials as well as possible break of the storage node electrodes, shortage problem of a lower area, etc.
Also, as shown in FIG. 1C, when storage node electrodes of a cylinder shape are formed, a bridge can be formed due to inclination of the pattern.